Synchronous systems and circuits, for example switch-mode power supplies (SMPS), microcontrollers, integrated digital/logic cores, etc. are often causing an undesired electromagnetic interference (EMI). Such systems and circuits are driven by a clock signal, which due to its periodic nature, creates an unavoidably narrow frequency spectrum and radiate electromagnetic energy across a number of narrow bands spread around the clock frequency as well as the clock frequency harmonics. This results in a frequency spectrum that, at certain frequencies, may exceed the regulatory limits for electromagnetic interference set, for example, by EMI standards e.g. CISPR-25, IEC 61967.
Spread-Spectrum Clock Generation (SSCG) is a technique that has been utilised in the art to help reduce this generated EMI. Generally, in SSCG, the clock frequency is modulated such that the same energy is spread out over a wider bandwidth, which prevents systems from placing enough energy into any one narrowband to exceed the statutory limits. In addition to potentially reducing any EMI from the fundamental system clock frequency, SSCG may also help attenuate EMI generated in successive clock harmonics.
There are a number of different types of oscillators that can be used in clocked systems. One such oscillator type, referred to as a switched current oscillator, is based on a capacitance charge/discharge process. Generally, in the art (e.g. U.S. Pat. No. 7,504,897), frequency modulation (via SSCG) of such oscillators is achieved by varying capacitance, current or voltage (supply voltage or switching threshold) at a speed that is similar to an oscillation frequency of the oscillator. Often modulation is performed by periodic signals (that are not perfect due to low frequency tones appearing causing EMI) or by pseudo-random signals generated by programmable pseudo-random number generators (PPRNG).
FIG. 1 illustrates a typical oscillator circuit for clock frequency spreading. Oscillator circuit 100 comprises current source 110, variable capacitor 120, PPRNG 130, FET 140 differential (input) comparator 150, flip-flop 160 and positive feedback capacitor C1. The differential comparator 150 compares sensed voltage 105 with reference voltage VREF. Oscillation happens by charging variable capacitance 120 by current source 110 until a voltage at node 105 reaches reference voltage VREF. Then comparator 150 switches and discharges variable capacitance 120 by FET 140. The voltage on node 105 then drops to zero and the comparator switches again, and so forth. FET 140 must discharge variable capacitor 130 quickly, as otherwise it affects the accuracy of the oscillator circuit 100. Further, in the oscillator circuit 100 of FIG. 1, flip flop 160 is required to provide a 50% duty cycle as only a single current source is utilised.
It is also known that current source 110 and FET 140 may be implemented as two current sources, each with a series switch (e.g. a FET) controlled in opposite phases by comparator 150. In these known implementations, a small capacitor (C1) is utilised to aid the differential comparator 150 in order to fully trip and to generate an appropriately shaped pulse.
Frequency modulation (through SSCG) is performed by varying the capacitance value provided by the variable capacitor 120, which is controlled by Programmable Pseudo-Random-Number Generator (PPRNG) 130 via a control signal (SYNC). The control signal is normally derived from an output of the oscillation circuit 100. A multiple-bit leap-forward linear feedback shift register (LFSR) is widely used for generation of pseudo random (for example in a PPRNG) or true random numbers in communication and encryption.
The implementation of variable capacitor 120 is problematic. For example, the overall capacitance of variable capacitor 120 needs to be relatively small for typically required oscillation frequencies. However, in contrast, a desire to provide ‘uniform’ clock frequency spreading by SSCG often requires a higher resolution of PPRNG (i.e. a relatively large number of bits being used). This requirement, together with the fact that a minimum reproducible value of unit capacitance is limited in integrated technologies, leads to a need to have a larger overall capacitance value for variable capacitor 120. As a result, this trade-off typically leads to increased cost and/or to increased power consumption in SSCG implementations. In addition, the resolution of a PPRNG and the possible clock spreading frequency bandwidth are closely inter-related, and it is therefore very difficult to modify either without affecting the other.
Alternatively, SSCG may also be implemented by modulation of a current (e.g. current source 110) or of a voltage (e.g. VREF modulation). Such implementations require current or voltage output, digital-to-analog converter (DAC) usage together with a PPRNG. This again leads to cost and/or to consumption increase.
U.S. Pat. No. 6,075,420 and U.S. Pat. No. 4,465,983 describe switched current oscillator circuits having a positive feedback capacitor that do not support SSCG.